1. Field of the invention
The present invention relates to a data transfer system for use in a computer system and, more particularly, to a data transfer system for performing direct data transfer efficiently from an input device having a first-in first-out (FIFO) memory, serving as a buffer, to a memory and from a memory to an output device having a first-in first-out (FIFO) memory serving as a buffer.
2. Description of the Related Art
Recent speeding-up and up-sizing of computer systems have enabled very big problems to be treated. Quantities of data to be treated have consequently become huge. Thus, the performance of computer systems is frequently influenced by input/output data rate. In a system configuration such as a parallel computer, large quantities of data are transferred between computing elements for information interchange.
In order to realize a high-speed computer system, it is required to input and output data faster and more efficiently than before.
In computer systems, direct memory access (DMA) systems are now widely used for direct data transfer between a memory and an input/output device without intervention of a central processing unit.
FIG. 1 (PRIOR ART) is a block diagram of a related art processor system using the DMA system. In this processor system, data is transferred from an input device 1 to a memory system 2 and from the memory system 2 to an output device 3 via a common bus 4 under the control of a direct memory access controller (DMAC) 5. A processor 6 is connected to the common bus 4 to control the entire system. The input device 1 is equipped with a first-in first-out (FIFO) memory 7 for storing input data and the output device 3 is equipped with a first-in first-out (FIFO) memory 8 for storing output data.
In FIG. 1, a request line 1 becomes active when data is present at the FIFO 7 of the input device 1, so that a request for transfer is sent to the DMAC 5. The DMAC 5 renders a memory write line 3 and a memory read line 2 active for data transfer. When there is free space in the FIFO 8 of the output device 3, a request line 4 becomes active, so that a request for transfer is sent to the DMAC 5. The DMAC 5 renders a memory read line 6 and a write line 5 active, so that data is transferred from the memory system 2 to the output device 3. The size of a unit of such data transfer is generally determined at the time of the initialization of the DMAC 5. For this reason, even if any number of pieces of data are present in the FIFO 7 of the input device 1 or any amount of free space is present in the FIFO 8 in the output device 3, data transfer is effected in a transfer unit the size of which was determined initially.
It is usual that, in realizing a memory system, transferable data sizes vary with access addresses of a memory and thus data transfer rates vary correspondingly. FIG. 2 (PRIOR ART) illustrates an example of a memory. In the Figure, one rectangular area represents 1-word data (4 bytes) storage area and digits within the rectangles represent addresses represented in decimal notation for simplicity.
In FIG. 2, four words can be transferred only from access addresses of 0, 16, 32, etc., and two words can be transferred from access addresses of 0, 8, 16, etc., but cannot be transferred from addresses 4, 12, etc. That transferable sizes of data vary with memory access addresses as described above is referred herein that the memory has address alignment.
FIG. 3 (PRIOR ART) illustrates specific examples of reading and writing properties of a memory system connected to a bus which is one word (four bytes) wide. In the Figure, there are shown transferable address alignment for 1-byte, 2-byte, 1-word, 2-word and 4-word data and the numbers of cycles required to transfer data of such sizes. Note that AX:Y! represents values of bits X to Y of an address.
The transfer of 1-byte data is possible with any address value and requires three cycles. The transfer of two-byte data is possible only when the 0 bit, or the low-order bit of an access address is 0 and requires three cycles.
The transfer of one-word data is possible only when the 0 and 1 bits, or the two low-order bits of an access address are 0s and requires three cycles. The transfer of four-word data is possible only when the four low-order bits of an access address are all 0s and requires six cycles. For example, if four-word data were transferred word by word, the number of cycles required would be 12. If, however, four words were transferred at a time, the number of cycles required would be six as described above.
In the related art described in connection with FIG. 1, the data size for transfer is previously determined. In order to transfer data most efficiently with as little a common-bus occupation time as possible, it is required to transfer data in a four-word unit with the reduced number of cycles indicated in FIG. 3. In this case, however, there are two conditions that address alignment must be correct and data must be transferred in multiples of four words. It is difficult to meet the two conditions for data transmission.